1. Field of the Invention
This invention relates to the clocking of electronic circuits, and more particularly, to the synchronization of multiple clock signals.
2. Description of the Related Art
In a typical computer system, one or more processors may communicate with input/output (I/O) devices over one or more buses. The I/O devices may be coupled to the processors through an I/O bridge which manages the transfer of information between a peripheral bus connected to the I/O devices and a shared bus connected to the processors. Additionally, the I/O bridge may manage the transfer of information between a system memory and the I/O devices or the system memory and the processors.
With multiple processors, multiple I/O devices, and multiple I/O bridges may come multiple clock domains. Often times, the clock frequencies required for operation of the processor, the I/O bridges, and the peripheral devices (and buses that couple these elements together) are different. Furthermore, it is often times possible the within a processor or an I/O bridge, multiple functional units may be present which require differing clock frequencies. In such cases, multiple clocks may be provided, with the clock signals being routed to their respective domains.
In systems having multiple clock domains, it is often necessary to transmit information from one domain to another. However, this is not a straightforward process when the clock frequencies from one domain to another are different. Often times a technique known as handshaking is used. Handshaking may involve a communication between two clock domains wherein an agreement is reached on when data may be sent. This may ensure that a faster domain does not overwhelm a slower domain by exceeding the maximum bandwidth of the slower domain. Similarly, handshaking may ensure that a slower device may utilize as much of the bandwidth of a faster domain as possible when the faster domain is receiving information.
Regardless of the technique used to transfer information between clock domains having different clock speeds, the relationship between the respective clock signals is an important consideration. In particular, it may be important to know the relationship between the rising or falling edges of the respective clock signals. Often times, it is difficult to ascertain this relationship. Thus, it may not always be possible to transmit information while utilizing the maximum available bandwidth on a link between two different clock domains.